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Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network.

, , , , , , , , and . IEEE Trans. Neural Networks Learn. Syst., 33 (7): 2853-2866 (2022)

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A variation-adaptive retiming method exploiting reconfigurability., , , , and . FPL, page 1-4. IEEE, (2013)Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory., , , and . FPT, page 56-63. IEEE, (2017)Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (12): 2307-2320 (2013)Classification on variation maps: a new placement strategy to alleviate process variation on FPGA., , , , and . IEICE Electron. Express, 11 (3): 20130912 (2014)Measuring and modeling FPGA clock variability., , and . FPGA, page 258. ACM, (2008)Self-Measurement of Combinatorial Circuit Delays in FPGAs., , and . ACM Trans. Reconfigurable Technol. Syst., 2 (2): 10:1-10:22 (2009)A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy., , , , and . IEEE Trans. Biomed. Circuits Syst., 13 (4): 781-792 (2019)A two-stage variation-aware placement method for FPGAS exploiting variation maps classification., , , , and . FPL, page 519-522. IEEE, (2012)Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting., , , , and . FPT, page 254-261. IEEE, (2013)High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing., , and . J. Imaging, 5 (3): 34 (2019)