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Disambiguation of "Cho, Yong Cheol Peter"

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A reconfigurable platform for the design and verification of domain-specific accelerators.

, , , and . ASP-DAC, page 108-113. IEEE, (2012)

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Yong-Cheol Kim

Yong Cheol Lim

Yong-Jig Cho

Sung-Yong Cho

Yong Suk Cho

 

Other publications of authors with the same name

A reconfigurable platform for the design and verification of domain-specific accelerators., , , and . ASP-DAC, page 108-113. IEEE, (2012)Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture., , , , , , , , , and . AICAS, page 127-131. IEEE, (2019)Chiplet Heterogeneous-Integration AI Processor., , , , , , , , , and 5 other author(s). ICEIC, page 1-2. IEEE, (2023)Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems., , , , , , and . ICCD, page 501-504. IEEE Computer Society, (2014)An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization., , , , , and . FCCM, page 41-48. IEEE Computer Society, (2011)A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics., , , and . A-SSCC, page 313-316. IEEE, (2017)ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System., , , , , , , , , and 2 other author(s). AICAS, page 466-468. IEEE, (2022)M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations., , , , , , , , , and . AICAS, page 150-153. IEEE, (2022)Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA., , , , and . FPL, page 311-316. IEEE Computer Society, (2011)Live Demonstration: A Neural Processor for AI Acceleration., , , , , , , , , and 2 other author(s). ISCAS, page 1. IEEE, (2021)