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Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers., and . IEEE J. Solid State Circuits, 42 (9): 1999-2011 (2007)A New Transceiver Architecture for the 60-GHz Band., and . IEEE J. Solid State Circuits, 44 (3): 751-762 (2009)A Low-Power CMOS Receiver for 5 GHz WLAN., and . IEEE J. Solid State Circuits, 50 (3): 630-643 (2015)Analysis of Metastability in Pipelined ADCs., and . IEEE J. Solid State Circuits, 49 (5): 1198-1209 (2014)Channel Selection at RF Using Miller Bandpass Filters., and . IEEE J. Solid State Circuits, 49 (12): 3063-3078 (2014)Heterodyne Phase Locking: A Technique for High-Frequency Division.. ISSCC, page 428-429. IEEE, (2007)A receiver architecture for intra-band carrier aggregation., and . VLSIC, page 1-2. IEEE, (2014)The future of radios.. ISCAS, page 1-8. IEEE, (2015)A 10-bit 1-GHz 33-mW CMOS ADC., and . VLSIC, page 30-31. IEEE, (2012)Phase-locking in wireline systems: Present and future.. CICC, page 615-622. IEEE, (2008)