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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.

, , , , , , и . ATS, стр. 149-154. IEEE, (2018)

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Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Joachim Wunderlich

Joachim Wunderlich

 

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Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen, , , , и . VDI-Buch Springer Berlin Heidelberg, Berlin, Heidelberg, (2009)Introduction., и . ACM Trans. Design Autom. Electr. Syst., 8 (4): 397-398 (2003)Efficient fault simulation on many-core processors., , , и . DAC, стр. 380-385. ACM, (2010)The design of random-testable sequential circuits.. FTCS, стр. 110-117. IEEE Computer Society, (1989)Minimized Power Consumption for Scan-Based BIST., и . J. Electron. Test., 16 (3): 203-212 (2000)Fast controllers for data dominated applications., и . ED&TC, стр. 84-89. IEEE Computer Society, (1997)Intelligent Methods for Test and Reliability., , , , , , , , , и 25 other автор(ы). DATE, стр. 969-974. IEEE, (2022)Robust Reconfigurable Scan Networks., , и . DATE, стр. 1149-1152. IEEE, (2022)Synthesis of IDDQ-testable circuits: integrating built-in current sensors., , , , и . ED&TC, стр. 573-580. IEEE Computer Society, (1995)Reliability Considerations forMechatronic Systems on the Basis of a State Model., , , и . ARCS Workshops, том P-41 из LNI, стр. 106-112. GI, (2004)