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A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.

, , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (6): 2114-2127 (2020)

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A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links., , , , and . IEEE J. Solid State Circuits, 58 (11): 3253-3265 (November 2023)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , and . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces., , , , and . ISSCC, page 1-3. IEEE, (2022)A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (6): 1862-1866 (2021)A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design., , , , , and . ICCAD, page 567-574. IEEE, (2015)A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec., , , , , , and . ESSCIRC, page 213-216. IEEE, (2022)A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces., , , , , , and . ISSCC, page 272-274. IEEE, (2018)A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (6): 2114-2127 (2020)An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching., , , , , , and . IEEE J. Solid State Circuits, 53 (6): 1780-1792 (2018)2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology., , , , , and . ISSCC, page 50-51. IEEE, (2014)