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TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer.

, , , , , and . DAC, page 1027-1032. IEEE, (2021)

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Early Development of Infant Brain Complex Network., , , , , , and . MICCAI (2), volume 11765 of Lecture Notes in Computer Science, page 832-840. Springer, (2019)FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 502-514 (2022)DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs., , , and . DAC, page 1-6. IEEE, (2020)Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC., , and . SoCC, page 56-61. IEEE, (2019)A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (6): 769-780 (2022)Multimodel Fusion Health Assessment for Multistate Industrial Robot via Fuzzy Deep Residual Shrinkage Network and Versatile Cluster., , , and . IEEE Trans. Fuzzy Syst., 32 (8): 4735-4746 (August 2024)WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization., , , , , and . ICCAD, page 142:1-142:9. ACM, (2022)TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer., , , , , and . DAC, page 1027-1032. IEEE, (2021)An Accurate FPGA Online Delay Monitor Supporting All Timing Paths., , , and . ISCAS, page 1-5. IEEE, (2020)Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS., , , and . ICECS, page 446-449. IEEE, (2019)