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Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design., , , , , , , и . ISCAS, стр. 1-5. IEEE, (2019)High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC., , , , , и . APCCAS, стр. 161-164. IEEE, (2020)Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic., , , , и . ISCAS, стр. 492-495. IEEE, (2012)Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process., , , , , , и . ISCAS, стр. 5-8. IEEE, (2016)An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations., , , , , , и . ISCAS, стр. 2256-2260. IEEE, (2022)Interceptive side channel attack on AES-128 wireless communications for IoT applications., , , и . APCCAS, стр. 650-653. IEEE, (2016)Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices., , , , , , , , , и 1 other автор(ы). Sensors, 22 (23): 9160 (2022)A comparative study on asynchronous Quasi-Delay-Insensitive templates., , , , , и . ISCAS, стр. 1819-1822. IEEE, (2012)A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline., , , , и . ISCAS, стр. 2589-2592. IEEE, (2015)A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications., , , , , , , и . ISCAS, стр. 1-5. IEEE, (2020)