( en | de | ru )

 

Disambiguation of "Shahsavani, Soheil Nazar"

Author of the publication

copydeleteadd this publication to your clipboard
Accurate margin calculation for single flux quantum logic cells.

, , and . DATE, page 509-514. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Soheil Pourrajabi

Nazar Mazurak

Soheil Asgari

Soheil Esfahanian

Soheil Samii

 

Other publications of authors with the same name

A heuristic machine learning-based algorithm for power and thermal management of heterogeneous MPSoCs., , , and . ISLPED, page 291-296. IEEE, (2015)A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits., , and . DATE, page 278-281. IEEE, (2020)A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement., , and . DATE, page 1465-1468. IEEE, (2018)A thermally-aware energy minimization methodology for global interconnects., , , and . DATE, page 1213-1218. IEEE, (2017)Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis., , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 17:1-17:25 (June 2023)Accurate margin calculation for single flux quantum logic cells., , and . DATE, page 509-514. IEEE, (2018)TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of Multipliers., and . DAC, page 1-6. IEEE, (2020)A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells., and . ISVLSI, page 645-650. IEEE, (2019)NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic., , , , , and . FCCM, page 266-267. IEEE, (2021)Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis., , , and . CoRR, (2022)