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A current-mode 6-9GHz UWB transmitter with output power flattening technique.

, , , , and . ISCAS, page 329-332. IEEE, (2010)

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A DLL based low-phase-noise clock multiplier with offset-tolerant PFD., , and . ASICON, page 1-4. IEEE, (2013)A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation., , , , and . APCCAS, page 128-131. IEEE, (2012)A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error., , and . ASICON, page 32-35. IEEE, (2017)A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs., , , , and . ASICON, page 295-298. IEEE, (2017)A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio., , , , , and . ISCAS, page 1145-1148. IEEE, (2011)Automatic gain control algorithm with high-speed and double closed-loop in UWB system., , , , and . ASICON, page 1-4. IEEE, (2013)A 22-40.5 GHz UWB LNA Design in 0.15um GaAs., , , , and . ASICON, page 1-4. IEEE, (2019)An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration., , and . Microelectron. J., (2018)A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (3): 127-131 (2013)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , and . APCCAS, page 42-45. IEEE, (2018)