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Hardware-Software Cosynthesis for Microcontrollers., , and . IEEE Des. Test Comput., 10 (4): 64-75 (1993)Simulation-Based Verification for High-Level Synthesis., and . IEEE Des. Test Comput., 8 (1): 14-20 (1991)Weakly-hard Real-time Guarantees for Earliest Deadline First Scheduling of Independent Tasks., , and . ACM Trans. Embed. Comput. Syst., 18 (6): 121:1-121:25 (2020)Response-Time Analysis for Task Chains with Complex Precedence and Blocking Relations., and . ACM Trans. Embed. Comput. Syst., 16 (5s): 172:1-172:19 (2017)Adaptive load distribution in mixed-critical Networks-on-Chip., , , and . ASP-DAC, page 732-737. IEEE, (2017)Real-time communication analysis for Networks-on-Chip with backpressure., and . DATE, page 590-595. IEEE, (2017)Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources., , and . DATE, page 524-529. IEEE, (2009)Panel session - Multicore, will Startups drive innovation?, and . DATE, page 1403. IEEE, (2009)Verifying Weakly-Hard Real-Time Properties of Traffic Streams in Switched Networks., , , and . ECRTS, volume 106 of LIPIcs, page 15:1-15:22. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2018)Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC., , and . ECRTS, volume 133 of LIPIcs, page 26:1-26:22. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2019)