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Disambiguation of "Zhou, Hai"

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An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.

, , , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (3): 36:1-36:23 (2018)

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Zhou Zhou

Zhou Zhou

Hai Li

Hai Li

Brigitte Hai

 

Other publications of authors with the same name

Circuit Retiming: An Incremental Approach.. Encyclopedia of Algorithms, (2016)Statistical Timing Yield Optimization by Gate Sizing., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (10): 1140-1146 (2006)Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (11): 2227-2235 (2014)A Common-Resonator Filtering Hybrid With a Wide Stopband and Compact Size., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (9): 3358-3362 (September 2023)Bandwidth-Aware Scheduling Repair Techniques in Erasure-Coded Clusters: Design and Analysis., , and . IEEE Trans. Parallel Distributed Syst., 33 (12): 3333-3348 (2022)Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 447-455 (2007)Spanning graph-based nonrectilinear steiner tree algorithms., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (7): 1066-1075 (2005)Simultaneous routing and buffer insertion with restrictions onbuffer locations., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 819-824 (2000)Gate-size optimization under timing constraints for coupling-noise reduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1064-1074 (2006)Binning Optimization for Transparently-Latched Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2): 270-283 (2011)