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An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS., , , , , , , , , and 10 other author(s). ISSCC, page 194-196. IEEE, (2021)Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM., , , , and . ISCAS, page 241-244. IEEE, (2012)9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz., , , , and . ISSCC, page 1-3. IEEE, (2015)Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs., , , , and . ISCAS, page 1225-1228. IEEE, (2007)A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping., , , , , , and . IEEE J. Solid State Circuits, 46 (6): 1371-1381 (2011)A novel output transformer based highly linear RF-DAC architecture., , , , and . ECCTD, page 1-4. IEEE, (2013)A novel timing-error based approach for high speed highly linear Mixing-DAC architectures., , , , and . ISCAS, page 942-945. IEEE, (2014)11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with., , , , , , , , , and 3 other author(s). ISSCC, page 206-207. IEEE, (2014)