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An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 113-126 (2017)

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Measurement-domain intra prediction framework for compressively sensed images., , , , and . ISCAS, page 1-4. IEEE, (2017)High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2519-2527 (2015)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing., , , and . IEICE Trans. Electron., 101-C (4): 263-272 (2018)A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 714-724 (2017)Energy-efficient scheduling method with cross-loop model for resource-limited CNN accelerator designs., , , and . ISCAS, page 1-4. IEEE, (2017)Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder., , , , and . PCM, volume 8879 of Lecture Notes in Computer Science, page 74-83. Springer, (2014)14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications., , , , , , , , , and 1 other author(s). ISSCC, page 266-268. IEEE, (2016)Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1356-1365 (2015)Approximate-DCT-derived measurement matrices for compressed sensing., , , and . ISCAS, page 1-4. IEEE, (2017)An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 52 (1): 113-126 (2017)