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Logic synthesis based on decomposition for CPLDs., and . Microprocess. Microsystems, 34 (1): 25-38 (2010)IEEE Access Special Section: Cyber-Physical Systems., , , , , and . IEEE Access, (2019)A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs., , and . DSD, page 114-121. IEEE Computer Society, (2005)State assignment and logic optimization for finite state machines., and . PDeS, page 39-44. International Federation of Automatic Control, (2009)A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs.. EUROMICRO, page 1146-. IEEE Computer Society, (2000)Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition.. EUROMICRO, page 1278-1281. IEEE Computer Society, (1999)Logic Decomposition for PAL-Based CPLDs.. Journal of Circuits, Systems, and Computers, 24 (3): 1550042:1-1550042:27 (2015)Logic synthesis of multi-output functions for PAL-based CPLDs.. FPT, page 429-432. IEEE, (2002)A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.. ACM Great Lakes Symposium on VLSI, page 152-155. ACM, (2007)Decomposition of Multi-Output Functions for CPLDs., , and . DSD, page 442-449. IEEE Computer Society, (2005)