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Disambiguation of "Jia, Haikun"

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A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology.

, , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Jia Jia

Jia Xu

Lina Jia

Jia Miao

Jia Zeng

 

Other publications of authors with the same name

International Solid-State Circuits Conference 2019 aims at "envisioning the future"., and . Sci. China Inf. Sci., 62 (6): 67401:1-67401:2 (2019)A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer., , , , , and . IEEE J. Solid State Circuits, 59 (1): 253-267 (January 2024)A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (11): 1839-1851 (November 2023)A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO., , , , and . A-SSCC, page 1-3. IEEE, (2023)An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator., , , , , , and . CICC, page 1-2. IEEE, (2021)A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers., , , , , , and . IEEE J. Solid State Circuits, 59 (5): 1323-1336 (May 2024)A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique., , , , , and . IEEE J. Solid State Circuits, 58 (10): 2861-2873 (October 2023)Optimization methods for high inductance-density inductors for high speed integrated circuits., , , , and . ICTA, page 243-244. IEEE, (2021)