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System-level test bench generation in a co-design framework.

, , , , и . ETW, стр. 25-30. IEEE Computer Society, (2000)

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Christian Lavagno

Luciano Trincia

Luciano Lazzaro

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Luciano Lampante

 

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Designing parameterized signal processing ips for high level synthesis in a model based design environment., и . CODES+ISSS, стр. 295-304. ACM, (2012)Enabling adaptability through elastic clocks., , и . DAC, стр. 8-10. ACM, (2009)A Fully-Automated Desynchronization Flow for Synchronous Circuits., , , и . DAC, стр. 982-985. IEEE, (2007)Guest Editors' Introduction: Trends and Directions in Microelectronics., и . IEEE Micro, 23 (3): 6-7 (2003)A software development tool chain for a reconfigurable processor., , и . CASES, стр. 93-98. ACM, (2001)Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis., , , и . IEEE Access, (2017)Modeling and Designing Heterogeneous Systems., , , , , и . Concurrency and Hardware Design, том 2549 из Lecture Notes in Computer Science, стр. 228-273. Springer, (2002)Coupling Asynchrony and Interrupts: Place Chart Nets., , , , , и . ICATPN, том 1248 из Lecture Notes in Computer Science, стр. 328-347. Springer, (1997)Wireless Sensor Networks., и . Handbook of Hardware/Software Codesign, (2017)Incremental high-level synthesis., , , , , , и . ASP-DAC, стр. 701-706. IEEE, (2010)