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Disambiguation of "Yoshimura, Takeshi"

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A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

, , , , and . DAC, page 299-304. ACM, (2004)

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Tateo Yoshimura

Takeshi Morita

Tadasuke Yoshimura

Takeshi Morita

Takeshi Imamura

 

Other publications of authors with the same name

Real-time video transport optimization using streaming agent over 3G wireless networks., , and . IEEE Trans. Multim., 7 (4): 777-785 (2005)A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2008)Register placement for high-performance circuits., , and . DATE, page 1470-1475. IEEE, (2009)Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis., , and . ASP-DAC, page 237-242. IEEE, (2013)Double feedback streaming agent for real-time delivery of media over 3G wireless networks., , and . WCNC, page 2102-2106. IEEE, (2003)Performance enhancement of TFI-OFDM with path selection based channel identification., , , , and . Digit. Signal Process., 19 (5): 852-860 (2009)Mobility overlap-removal based leakage power aware scheduling in high-level synthesis., , , and . ISCAS, page 1745-1748. IEEE, (2013)Power and resource aware scheduling with multiple voltages., , , , and . ASICON, page 1-4. IEEE, (2013)Floorplanning driven Network-on-Chip synthesis for 3-D SoCs., , , , and . ISCAS, page 1203-1206. IEEE, (2011)Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis., , , and . ASICON, page 1-4. IEEE, (2015)