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Disambiguation of "Roy, Kaushik"

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Process variation in nano-scale memories: failure analysis and process tolerant architecture.

, , and . CICC, page 353-356. IEEE, (2004)

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Kaushik Bhaganagarapu

Kaushik Biswas

Kaushik Ravichandran

Kaushik Mitra

Kaushik Banik

 

Other publications of authors with the same name

A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime., and . ISLPED, page 18-21. ACM, (2003)Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications., , and . DAC, page 21:1-21:6. ACM, (2016)M2CA: Modular Memristive Crossbar Arrays., , , and . ISCAS, page 1-5. IEEE, (2018)Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS., , , and . IEEE J. Solid State Circuits, 42 (6): 1370-1382 (2007)DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data., and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 624-634 (2018)Towards Understanding the Effect of Leak in Spiking Neural Networks., , and . CoRR, (2020)An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain., , , and . IEEE Trans. Emerg. Top. Comput. Intell., 2 (5): 345-358 (2018)Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (9): 1034-1039 (2006)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1286-1295 (2005)Spike-FlowNet: Event-Based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks., , , , , and . ECCV (29), volume 12374 of Lecture Notes in Computer Science, page 366-382. Springer, (2020)