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ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations.

, , , , , and . ASICON, page 16-19. IEEE, (2017)

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Novel RRAM programming technology for instant-on and high-security FPGAs., , , , , and . ASICON, page 291-294. IEEE, (2011)Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing., , , , , and . ASICON, page 1-4. IEEE, (2013)Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 186-190 (2017)A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 336-340 (2016)3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance., , , and . ISCAS, page 377-380. IEEE, (2015)A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application., , , , and . ISCAS, page 1-4. IEEE, (2017)A low cost and high reliability true random number generator based on resistive random access memory., , , , , , , and . ASICON, page 1-4. IEEE, (2015)Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform., , , , , and . ASICON, page 1-4. IEEE, (2015)A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction., , , , , , , , , and 1 other author(s). VLSIC, page 42-43. IEEE, (2012)ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations., , , , , and . ASICON, page 16-19. IEEE, (2017)