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Disambiguation of "Calazans, Ney Laert Vilar"

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Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?

, , , and . LATW, page 1-5. IEEE, (2014)

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Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Evaluating the scalability of test buses., , , , , and . ISSoC, page 1-6. IEEE, (2013)A processor for IoT applications: An assessment of design space and trade-offs., , , , and . Microprocess. Microsystems, (2016)A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 15:1-15:23 (2016)Static Differential NCL Gates: Toward Low Power., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (6): 563-567 (2015)A path towards average-case silicon via asynchronous resilient bundled-data design., and . ECCTD, page 1-4. IEEE, (2015)XGT4: An industrial grade, open source tester for multi-gigabit networks., , , , and . ICECS, page 252-255. IEEE, (2017)A generic FPGA emulation framework., , , , , , , and . ICECS, page 233-236. IEEE, (2012)TDTB error detecting latches: Timing violation sensitivity analysis and optimization., , , and . ISQED, page 379-383. IEEE, (2015)Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis., , , and . ACM Great Lakes Symposium on VLSI, page 3-8. ACM, (2014)Charge sharing aware NCL gates design., , , and . DFTS, page 212-217. IEEE Computer Society, (2013)