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Disambiguation of "Toyoda, Hidehiro"

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A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet.

, , , and . ICC, page 5417-5421. IEEE, (2008)

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Minoru Toyoda

 

Other publications of authors with the same name

A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet., , and . ICC, page 1-6. IEEE, (2011)Simultaneous multi-ONU wavelength switching method for coexistence of different λ-tuning times in WDM/TDM-PON., , and . OFC, page 1-3. IEEE, (2015)Adaptive FEC control in downstream collaborating with traffic control in OLT for WDM/TDM-PON., , and . ECOC, page 1-3. IEEE, (2015)A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 106-107. IEEE, (2012)A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications., , , and . IEICE Trans. Electron., 90-C (10): 1957-1963 (2007)A 100-Gb-Ethernet subsystem for next-generation metro-area network., , , , and . ICC, page 1036-1042. IEEE, (2005)100GbE PHY and MAC layer implementations., , and . IEEE Communications Magazine, (2010)10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link., , , , , , , , , and 5 other author(s). ISSCC, page 148-150. IEEE, (2011)A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology., , , and . IEICE Trans. Commun., 95-B (11): 3437-3444 (2012)A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet., , , and . ICC, page 5417-5421. IEEE, (2008)