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Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays.

Y. Lu, L. Liu, Y. Deng, J. Weng, S. Yin, Y. Shi, and S. Wei. IEEE Trans. Parallel Distributed Syst., 29 (10): 2360-2372 (2018)

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Shaojun Lu

Shaojun Tong

Wei Wei

Other publications of authors with the same name

Affine transformations for communication and reconfiguration optimization of loops on CGRAs.D. Liu, S. Yin, L. Liu, and S. Wei. ISCAS, page 2541-2544. IEEE, (2013)Memory fartitioning-based modulo scheduling for high-level synthesis.T. Lu, S. Yin, X. Yao, Z. Xie, L. Liu, and S. Wei. ISCAS, page 1-4. IEEE, (2017)Reconfigurable computing - evolution of Von Neumann architecture.S. Wei. FPT, IEEE, (2010)A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.L. Wang, P. Lv, L. Liu, J. Han, H. fung Leung, X. Wang, S. Yin, S. Wei, and T. Mak. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1771-1784 (2019)Efficient Scheduling of Irregular Network Structures on CNN Accelerators.S. Zheng, X. Zhang, D. Ou, S. Tang, L. Liu, S. Wei, and S. Yin. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3408-3419 (2020)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.S. Liang, S. Yin, L. Liu, Y. Guo, and S. Wei. IEEE Comput. Archit. Lett., 15 (2): 69-72 (2016)A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection.G. Peng, L. Liu, S. Zhou, S. Yin, and S. Wei. IEEE J. Solid State Circuits, 55 (2): 505-519 (2020)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, and S. Yin. IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction.H. Mo, W. Zhu, W. Hu, Q. Li, A. Li, S. Yin, S. Wei, and L. Liu. IEEE J. Solid State Circuits, 57 (5): 1542-1557 (2022)UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.X. Chen, B. Yang, J. Zhu, J. Liu, S. Yin, G. Yang, M. Zhu, S. Wei, and L. Liu. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024 (2): 677-713 (2024)

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Disambiguation of "Wei, Shaojun"

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation