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Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects., , , , , , , и . IRPS, стр. 1-5. IEEE, (2020)Variation-aware Fault Modeling and Test Generation for STT-MRAM., , , , и . IOLTS, стр. 80-83. IEEE, (2019)Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis., , , , , , , , и . VTS, стр. 1-10. IEEE, (2020)Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory., , и . ETS, стр. 1-6. IEEE, (2020)Dynamic Faults based Hardware Trojan Design in STT-MRAM., , , и . DATE, стр. 933-938. IEEE, (2020)Mitigating Read Failures in STT-MRAM., , и . VTS, стр. 1-6. IEEE, (2020)Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic Memories. Karlsruhe University, Germany, (2020)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:1000119696).VAET-STT: A variation aware estimator tool for STT-MRAM based memories., , , , и . DATE, стр. 1456-1461. IEEE, (2017)Using multifunctional standardized stack as universal spintronic technology for IoT., , , , , , , , , и 8 other автор(ы). DATE, стр. 931-936. IEEE, (2018)A Universal Spintronic Technology based on Multifunctional Standardized Stack., , , , , , , , и . DATE, стр. 394-399. IEEE, (2020)