Author of the publication

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2737-2747 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1342-1350 (2016)Si–Mn/Reduced Graphene Oxide Nanocomposite Anodes with Enhanced Capacity and Stability for Lithium-Ion Batteries, , , , , , , and . ACS Applied Materials & Interfaces, 6 (3): 1702-1708 (2014)PMID: 24443772.One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation., , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (5): 1551-1561 (2020)An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache., , , , , and . IEEE Access, (2020)Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation., , , , and . IEEE Access, (2021)Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 964-968 (2016)Shape Analysis of Euclidean Curves under Frenet-Serret Framework., , and . ICCV, page 4004-4013. IEEE, (2023)High-Order Tensor Regularization With Application to Attribute Ranking., , and . CVPR, page 4349-4357. Computer Vision Foundation / IEEE Computer Society, (2018)Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time., , , and . IEEE J. Solid State Circuits, 54 (8): 2304-2315 (2019)New flash memory acquisition methods based on firmware update protocols for LG Android smartphones., , and . Digital Investigation, (2018)