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HARP: hard-wired routing pattern FPGAs., , , , , and . FPGA, page 21-29. ACM, (2005)Binary stochastic implementation of digital logic., , and . FPGA, page 171-180. ACM, (2014)Fast and accurate estimation of floorplans in logic/high-level synthesis., , and . ACM Great Lakes Symposium on VLSI, page 95-100. ACM, (2000)Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory., , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 3189 of Lecture Notes in Computer Science, page 88-101. Springer, (2004)An Overview of Time-Based Computing with Stochastic Constructs., , , , , and . IEEE Micro, 37 (6): 62-71 (2017)Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures., , and . DAC, page 635-640. ACM, (2001)Microarchitecture floorplanning for sub-threshold leakage reduction., and . DATE, page 1238-1243. EDA Consortium, San Jose, CA, USA, (2007)A fast SPFD-based rewiring technique., and . ASP-DAC, page 55-60. IEEE, (2010)A generalized and unified SPFD-based rewiring technique., and . FPL, page 305-310. IEEE, (2007)Three-dimensional place and route for FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1132-1140 (2006)