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Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.

, and . IEEE Des. Test Comput., 22 (5): 399-403 (2005)

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Testability Measures : What Do They Do for ATPG ?, and . ITC, page 129-139. IEEE Computer Society, (1986)Analog IP design flow for SoC applications., , , and . ISCAS (4), page 676-679. IEEE, (2003)Effect of traffic localization on energy dissipation in NoC-based interconnect., , , , and . ISCAS (2), page 1774-1777. IEEE, (2005)A new decompressor with ordered parallel scan design for reduction of test data and test time., , , and . ISCAS, page 641-644. IEEE, (2015)Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems.. IEEE Des. Test, 31 (6): 4-5 (2014)Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits., , , , , , and . J. Electron. Test., 25 (1): 55-66 (2009)Testing for Floating Gates Defects in CMOS Circuits., , , and . Asian Test Symposium, page 228-236. IEEE Computer Society, (1998)Design of an Optimal Test Access Architecture Using a Genetic Algorithm., and . Asian Test Symposium, page 205-. IEEE Computer Society, (2001)A Current Integrator for BIST of Mixed-Signal ICs., and . VTS, page 311-318. IEEE Computer Society, (1999)Minimal hardware multiple signature analysis for BIST., and . VTS, page 17-20. IEEE Computer Society, (1993)