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Real-time HD image distortion correction in heterogeneous parallel computing systems using efficient memory access patterns., , and . J. Real-Time Image Processing, 11 (1): 83-91 (2016)Flexible non-binary LDPC decoding on FPGAs., , , and . ICASSP, page 1936-1940. IEEE, (2014)Scalable and parallel codec architectures for the DVB-S2 FEC system., , , , , , , and . APCCAS, page 1506-1509. IEEE, (2008)How GPUs can outperform ASICs for fast LDPC decoding., , and . ICS, page 390-399. ACM, (2009)Parallel LDPC Decoding on the Cell/B.E. Processor., , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 389-403. Springer, (2009)Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design., , , , and . EURASIP J. Wireless Comm. and Networking, (2012)Massively LDPC Decoding on Multicore Architectures., , and . IEEE Trans. Parallel Distributed Syst., 22 (2): 309-322 (2011)Exploiting Compute Caches for Memory Bound Vector Operations., , , , and . SBAC-PAD, page 197-200. IEEE, (2018)Flexible Parallel Architecture for DVB-S2 LDPC Decoders., , , , , and . GLOBECOM, page 3265-3269. IEEE, (2007)Optimized Fast Walsh-Hadamard Transform on GPUs for non-binary LDPC decoding., , and . Parallel Comput., 40 (9): 449-453 (2014)