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Disambiguation of "Kolagotla, Ravi K."

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A 333-MHz dual-MAC DSP architecture for next-generation wireless applications.

, , , , , , , , and . ICASSP, page 1013-1016. IEEE, (2001)

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Ravi Walli

Mylapore Ravi

Holger Raviol

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Fausto Ravida

 

Other publications of authors with the same name

Systolic architectures for finite-state vector quantization., , and . J. VLSI Signal Process., 5 (2-3): 249-259 (1993)Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms., , , and . ICASSP (3), page 73-76. IEEE Computer Society, (1993)Addressing mode driven low power data caches for embedded processors., , and . WMPI, page 129-135. ACM, (2004)Introduction to the Special Issue on the IEEE 2006 Custom Integrated Circuits Conference., , and . IEEE J. Solid State Circuits, 42 (8): 1633-1634 (2007)High performance dual-MAC DSP architecture., , , , , , , , and . IEEE Signal Process. Mag., 19 (4): 42-53 (2002)Systolic architectures for finite-state vector quantization., , and . ASAP, page 481-495. IEEE, (1992)A 333-MHz dual-MAC DSP architecture for next-generation wireless applications., , , , , , , , and . ICASSP, page 1013-1016. IEEE, (2001)Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms., , , and . IEEE Trans. Circuits Syst. Video Technol., 4 (2): 168-180 (1994)Design and Implementation of Systolic Architectures for Vector Quantization.. University of Maryland, College Park, MD, USA, (1992)base-search.net (ftunivmaryland:oai:drum.lib.umd.edu:1903/5319).VLSI implementation of a tree searched vector quantizer., , and . IEEE Trans. Signal Process., 41 (2): 901-905 (1993)