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DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor.

, , , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)

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Ishwar Nath Topa

Ishwar Singh Dagar

 

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Panel: Reliability of data centers: Hardware vs. software., , , , , и . DATE, стр. 1620. IEEE Computer Society, (2010)A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors., , , , и . ITC, стр. 726-735. IEEE Computer Society, (2002)Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field., , , и . ITC, стр. 9. IEEE Computer Society, (2005)Lower Bounds on Test Resources for Scheduled Data Flow Graphs., , и . DAC, стр. 143-148. ACM Press, (1996)Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems., , , , и . ITC, стр. 8. IEEE Computer Society, (2005)Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors., , , , и . ETS, стр. 33-38. IEEE Computer Society, (2009)Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead., , и . DAC, стр. 395-401. ACM Press, (1995)Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST., , и . DAC, стр. 345-356. ACM Press, (1994)Silent Data Corruption - Myth or reality?, , , и . DSN, стр. 108-109. IEEE Computer Society, (2008)Introducing Redundant Computations in a Behavior for Reducing BIST Resources., , и . DAC, стр. 548-553. ACM Press, (1998)