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Disambiguation of "Parulkar, Ishwar"

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Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.

, , , , and . ITC, page 8. IEEE Computer Society, (2005)

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Ishwar Nath Topa

Ishwar Singh Dagar

 

Other publications of authors with the same name

Panel: Reliability of data centers: Hardware vs. software., , , , , and . DATE, page 1620. IEEE Computer Society, (2010)A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors., , , , and . ITC, page 726-735. IEEE Computer Society, (2002)Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field., , , and . ITC, page 9. IEEE Computer Society, (2005)Lower Bounds on Test Resources for Scheduled Data Flow Graphs., , and . DAC, page 143-148. ACM Press, (1996)Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST., , and . DAC, page 345-356. ACM Press, (1994)Silent Data Corruption - Myth or reality?, , , and . DSN, page 108-109. IEEE Computer Society, (2008)Introducing Redundant Computations in a Behavior for Reducing BIST Resources., , and . DAC, page 548-553. ACM Press, (1998)Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors., , , , and . ETS, page 33-38. IEEE Computer Society, (2009)Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead., , and . DAC, page 395-401. ACM Press, (1995)Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems., , , , and . ITC, page 8. IEEE Computer Society, (2005)