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Ultimate: A hardware logic simulation engine., and . DAC, page 336-342. ACM/IEEE, (1984)A Steady-State Response Test Generation for Mixed-Signal Integrated Circuits., , and . ITC, page 415-421. IEEE Computer Society, (1992)Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI., , , , and . ITC, page 232-243. IEEE Computer Society, (1986)Economic Effects in Design and Test., , , and . IEEE Des. Test Comput., 8 (4): 64-77 (1991)Behavioral Test Economics., , and . ITC, page 1-9. IEEE Computer Society, (2006)Is It Rocket Science?. ITC, page 1188-1189. IEEE Computer Society, (2002)The Economics of System-Level Testing., and . IEEE Des. Test Comput., 14 (3): 51-58 (1997)The application and use of boundary scan: Bleeker, H, van den Eijnden, P and de Jong, FBoundary-scan test - a practical approach Kluwer Academic (1992) ISBN 0 7923 9296 5, £50.75, pp 222.. Microprocess. Microsystems, 17 (5): 305 (1993)Design Trade-Offs and Power Reduction Techniques for High Performance Circuits and System., and . ICCSA (5), volume 3984 of Lecture Notes in Computer Science, page 531-536. Springer, (2006)Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards., , , , and . ITC, page 210-217. IEEE Computer Society, (1993)