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Disambiguation of "Boemo, Eduardo I."

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A-B Nodes Classification for Power Estimation.

, and . FPL, page 1-6. IEEE, (2006)

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Nata i i

Eduardo Ospina

Eduardo Klein

Eduardo Maurô

Eduardo Monari

 

Other publications of authors with the same name

Some experiments about wave pipelining on FPGA's., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (2): 232-237 (1998)Power Aware Dividers in FPGA., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 574-584. Springer, (2004)Statistical Power Estimation for FPGA., , , and . FPL, page 515-518. IEEE, (2005)A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation., , , , and . ICECS, page 241-244. IEEE, (1999)Rapid prototyping of a self-timed ALU with FPGAs., , , and . ReConFig, IEEE Computer Society, (2005)A-B Nodes Classification for Power Estimation., and . FPL, page 1-6. IEEE, (2006)FSM Decomposition for Low Power in FPGA., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 350-359. Springer, (2002)Design and FPGA implementation of digit-serial FIR filters., , , and . ICECS, page 191-194. IEEE, (1998)The Wave Pipeline Effect on LUT-Based FPGA Architectures., , and . FPGA, page 45-50. ACM, (1996)Thermal Testing on Reconfigurable Computers., , and . IEEE Des. Test Comput., 17 (1): 84-91 (2000)