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Disambiguation of "Ahn, Jung Ho"

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CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory.

, , , , , and . DATE, page 33-38. IEEE, (2012)

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Bong-Ho Ahn

Ahn-Jung Song

Ho-Jung Hwang

Ki-Ho Jung

Jung Ho Kim

 

Other publications of authors with the same name

Replication-aware leakage management in chip multiprocessors with private L2 cache., , and . ISLPED, page 135-140. ACM, (2010)SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling., , , , , , and . HPCA, page 333-346. IEEE, (2023)Human Silhouette Extraction Method Using Region Based Background Subtraction., and . MIRAGE, volume 4418 of Lecture Notes in Computer Science, page 412-420. Springer, (2007)An Integrated Robot Vision System for Multiple Human Tracking and Silhouette Extraction., , , , and . ICAT, volume 4282 of Lecture Notes in Computer Science, page 575-583. Springer, (2006)BCD deduplication: effective memory compression using partial cache-line deduplication., , , , and . ASPLOS, page 52-64. ACM, (2021)TWiCe: preventing row-hammering by exploiting time window counters., , , , and . ISCA, page 385-396. ACM, (2019)HyPHEN: A Hybrid Packing Method and Its Optimizations for Homomorphic Encryption-Based Neural Networks., , , , and . IEEE Access, (2024)TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory., , , , , and . MICRO, page 268-281. ACM, (2021)Tradeoff between data-, instruction-, and thread-level parallelism in stream processors., , and . ICS, page 126-137. ACM, (2007)Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os., , , , , , and . ICCAD, page 747-754. IEEE, (2013)