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Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations., , and . HEART, page 17:1-17:5. ACM, (2018)Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs., , , and . IET Comput. Digit. Tech., 12 (6): 251-257 (2018)A Lightweight McEliece Cryptosystem Co-processor Design., , , and . CoRR, (2019)PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures., , and . ACM Great Lakes Symposium on VLSI, page 65-70. ACM, (2017)ClosNets: a Priori Sparse Topologies for Faster DNN Training., and . CoRR, (2018)Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators., , , and . AsianHOST, page 62-67. IEEE, (2018)CodeTrolley: Hardware-Assisted Control Flow Obfuscation., , and . CoRR, (2019)Janus: An uncertain cache architecture to cope with side channel attacks., , , , and . MWSCAS, page 827-830. IEEE, (2017)A Taxonomy of Error Sources in HPC I/O Machine Learning Models., , , , , , , , and . SC, page 16:1-16:14. IEEE, (2022)Towards Programmable All-Digital True Random Number Generator., , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2020)