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An Improved Logarithmic Multiplier for Media Processing.

, and . J. Signal Process. Syst., 91 (6): 561-574 (2019)

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A new approach to minimize leakage power in nano-scale VLSI adder., , , and . ICWET, page 880-886. ACM, (2010)A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits, and . CoRR, (2006)A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application., , , and . IEEE J. Solid State Circuits, 53 (10): 2951-2957 (2018)A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements., , , and . EMBC, page 3844-3847. IEEE, (2017)Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations., , , and . ESA, page 160-168. CSREA Press, (2006)Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs., and . Nano-Net, page 25. ICST/ACM, (2007)A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC., , and . VLSI-SoC, page 252-257. IEEE, (2007)Delay and Energy Efficient Coding Techniques for Capacitive Interconnects., and . Journal of Circuits, Systems, and Computers, 16 (6): 929-942 (2007)A Generic Architecture for Intelligent System Hardware., and . APCCAS, page 321-326. IEEE, (2006)A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects., and . DSD, page 325-330. IEEE Computer Society, (2007)