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Disambiguation of "Ye, Le"

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Widely reconfigurable 8th-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS.

, , , , and . ISCAS, page 672-675. IEEE, (2012)

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Fei Ye

Ye Hu

Ye Chen

Ying Ye

Wei Ye

 

Other publications of authors with the same name

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter., , , , and . ISCAS, page 749-752. IEEE, (2013)Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (1): 95-107 (2013)A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (9): 2804-2816 (2021)An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (8): 3075-3088 (2023)Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 1160-1170 (2021)A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes., and . Microelectron. J., (2022)A single-chip CMOS UHF RFID Reader transceiver for mobile applications., , , , , , , , , and 2 other author(s). ESSCIRC, page 228-231. IEEE, (2009)A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology., , , , , , , , , and . ESSCIRC, page 121-124. IEEE, (2023)A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing., , , , , , , , , and 3 other author(s). ISSCC, page 140-141. IEEE, (2023)30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing., , , , , , , , , and 1 other author(s). ISSCC, page 484-486. IEEE, (2024)