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Disambiguation of "Psarras, Anastasios"

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A Dual-Clock Multiple-Queue Shared Buffer.

, , , and . IEEE Trans. Computers, 66 (10): 1809-1815 (2017)

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Anastasios Giannitsis

Anastasios Moissidis

Anastasios Maniatoglou

Anastasios Giannakis

Anastasios Pantasidis

 

Other publications of authors with the same name

ElastiStore: An elastic buffer architecture for Network-on-Chip routers., , , and . DATE, page 1-6. European Design and Automation Association, (2014)CrossOver: Clock domain crossing under virtual-channel flow control., , , and . DATE, page 1183-1188. IEEE, (2016)ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture., , , , and . NOCS, page 135-142. IEEE, (2014)Hardware primitives for the synthesis of multithreaded elastic systems., , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Virtual-Channel Flow Control Across Mesochronous Clock Domains., , and . MOCAST, page 1-4. IEEE, (2022)Networks-on-Chip With Double-Data-Rate Links., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3103-3114 (2017)11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge., , , , , , , , , and 38 other author(s). ISSCC, page 212-214. IEEE, (2024)Timing-resilient Network-on-Chip architectures., , , and . IOLTS, page 77-82. IEEE, (2015)Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project., , , , , , , and . IEEE Access, (2017)A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors., , , , and . ACM Great Lakes Symposium on VLSI, page 335-340. ACM, (2016)