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Disambiguation of "Shibata, Nobutaro"

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A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation.

, , and . IEICE Trans. Electron., 88-C (4): 582-588 (2005)

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Daisuke Shibata

Tomohiro Shibata

 

Other publications of authors with the same name

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme., , , , , and . IEEE J. Solid State Circuits, 41 (3): 728-742 (2006)A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells., , and . IEEE J. Solid State Circuits, 45 (9): 1856-1869 (2010)A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers., , and . IEEE J. Solid State Circuits, 34 (6): 866-877 (1999)A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell., , and . IEEE J. Solid State Circuits, 37 (6): 735-750 (2002)High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (8): 1415-1428 (2015)A 1-V 1-Mb SRAM for portable equipment., and . ISLPED, page 61-66. IEEE, (1996)An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (8): 1185-1196 (2018)A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications., , and . IEICE Trans. Electron., 99-C (6): 717-726 (2016)A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation., , and . IEICE Trans. Electron., 88-C (4): 582-588 (2005)A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs., , , , and . IEEE J. Solid State Circuits, 36 (10): 1524-1537 (2001)