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At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.

, , , , and . VLSI Design, page 895-900. IEEE Computer Society, (2004)

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Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , and . DAC, page 535-540. IEEE Computer Society Press, (1990)Differential Fault Simulation - a Fast Method Using Minimal Memory., and . DAC, page 424-428. ACM Press, (1989)Improve speed path identification with suspect path expressions., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Diagnosing timing related cell internal defects for FinFET technology., , , , and . VLSI-DAT, page 1-4. IEEE, (2015)Emulating and diagnosing IR-drop by using dynamic SDF., , , , and . ASP-DAC, page 511-516. IEEE, (2010)On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs., , , and . ETS, page 1-2. IEEE, (2014)Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis., , , , , , , , , and 1 other author(s). ITC, page 1-9. IEEE Computer Society, (2006)Diagnosis with Limited Failure Information., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)On Improving Diagnostic Test Generation for Scan Chain Failures., , , , and . Asian Test Symposium, page 41-46. IEEE Computer Society, (2009)On Using Design Partitioning to Reduce Diagnosis Memory Footprint., , , , and . Asian Test Symposium, page 219-225. IEEE Computer Society, (2011)