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Disambiguation of "Agarwal, Amit"

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Low-power design techniques for scaled technologies.

, , and . Integr., 39 (2): 64-89 (2006)

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Amit Agarwal

Regina Amith-Borchart

Menachem Amitai

Samuel Amiteye

Menachem Amitai

 

Other publications of authors with the same name

Co- Location Resistant Virtual Machine Placement in Cloud Data Centers., and . ICPADS, page 61-68. IEEE, (2018)Near-threshold voltage (NTV) design: opportunities and challenges., , , , , and . DAC, page 1153-1158. ACM, (2012)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , and . ESSCIRC, page 177-180. IEEE, (2012)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , and . VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Jupiter Rising: A Decade of Clos Topologies and Centralized Control in Google's Datacenter Network., , , , , , , , , and 8 other author(s). SIGCOMM, page 183-197. ACM, (2015)On-Chip High-Resolution Timing Characterization Circuits for Memory IPs., , , , , , and . ESSCIRC, page 377-380. IEEE, (2022)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)Agent-based Simultaneous Optimization of Congestion and Air Pollution: A Real-World Case Study., and . ANT/SEIT, volume 52 of Procedia Computer Science, page 914-919. Elsevier, (2015)