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Disambiguation of "Huang, Wei-Hsing"

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A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.

, , , , , , , , , , , , , , , and . A-SSCC, page 217-218. IEEE, (2019)

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Wei Huang

Chao-Huang Wei

Wei-Teh Huang

Wei-Tung Huang

Wenjung Hsing

 

Other publications of authors with the same name

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 58 (3): 877-892 (March 2023)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors., , , , , , , , , and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 59 (1): 116-127 (January 2024)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits., and . IEEE Trans. Instrumentation and Measurement, 47 (2): 426-431 (1998)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , and . DAC, page 1-6. IEEE, (2020)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)Test points selection process and diagnosability analysis of analog integrated circuits., and . ICCD, page 582-587. IEEE Computer Society, (1998)