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An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design, , , and . CoRR, (2009)Design of multi-stage latency adders using detection and sequence-dependence between successive calculations., , , , and . ISCAS, page 998-1001. IEEE, (2014)Hardware acceleration with pipelined adder for Support Vector Machine classifier., , , and . DICTAP, page 13-16. IEEE, (2014)Multi-robot coordination for high-speedpick-and-place tasks., , , and . ROBIO, page 1743-1750. IEEE, (2017)基于BP神经网络的就业招聘企业客户分类问题研究 (Customer Classification Model of Employers by Using BP Neural Networks)., and . 计算机科学, 42 (Z11): 1-4 (2015)Balanced Switching Schemes for Gradient-Error Compensation in Current-Steering DACs., , , and . IEICE Trans. Electron., 95-C (11): 1790-1798 (2012)ACO-Based Scheduling of Parallel Batch Processing Machines with Incompatible Job Families to Minimize Total Weighted Tardiness., , and . ANTS Conference, volume 5217 of Lecture Notes in Computer Science, page 219-226. Springer, (2008)Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine., , and . Multimedia Tools Appl., 56 (3): 597-614 (2012)ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (1): 198-211 (2020)