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Disambiguation of "Li, Xiaowei"

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Diagnosis and Layout Aware (DLA) scan chain stitching.

, , , , , , , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)

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Xiaowei Wu

Xiaowei Lan

Xiaowei Xu

Xiaowei Chen

Xiaowei Ding

 

Other publications of authors with the same name

A Loop-Based Apparatus for At-Speed Self-Testing., and . J. Comput. Sci. Technol., 16 (3): 278-285 (2001)Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time., , , , and . IEICE Trans. Inf. Syst., 89-D (10): 2616-2625 (2006)BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission., , , and . IEICE Trans. Electron., 91-C (10): 1690-1697 (2008)A Novel Post-Silicon Debug Mechanism Based on Suspect Window., , and . IEICE Trans. Inf. Syst., 93-D (5): 1175-1185 (2010)Data Remapping for Static NUCA in Degradable Chip Multiprocessors., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 879-892 (2015)New Methodologies for Parallel Architecture., , and . J. Comput. Sci. Technol., 26 (4): 578-587 (2011)DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning., , , , , and . J. Supercomput., 79 (3): 2819-2849 (2023)Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1787-1800 (2011)Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 92-102 (2016)Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2476-2487 (2014)