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Low Voltage Clock Tree Synthesis with Local Gate Clusters.

, , , and . ACM Great Lakes Symposium on VLSI, page 99-104. ACM, (2019)

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Enhanced level shifter for multi-voltage operation., , , and . ISCAS, page 1442-1445. IEEE, (2015)Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks., , , and . ACM Great Lakes Symposium on VLSI, page 283-288. ACM, (2015)Skew-bounded low swing clock tree optimization., and . ACM Great Lakes Symposium on VLSI, page 49-54. ACM, (2013)A Novel Static D-Flip-Flop Topology for Low Swing Clocking., , , , and . ACM Great Lakes Symposium on VLSI, page 301-306. ACM, (2015)SLECTS: Slew-Driven Clock Tree Synthesis., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 864-874 (2019)A microcontroller-based embedded system design course with PSoC3., , and . MSE, page 28-31. IEEE Computer Society, (2013)Multi-voltage domain clock mesh design., and . ICCD, page 201-206. IEEE Computer Society, (2012)Multi-corner multi-voltage domain clock mesh design., and . ACM Great Lakes Symposium on VLSI, page 209-214. ACM, (2013)Iterative skew minimization for low swing clocks., and . Integr., 47 (3): 356-364 (2014)High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design., , , and . ISVLSI, page 498-503. IEEE Computer Society, (2014)