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Disambiguation of "Loi, Igor"

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Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 210-223 (2017)

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Hugo Loi

Simona Loi

Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Phuc-Loi Luu

Tran Loi Chung

 

Other publications of authors with the same name

A shared-FPU architecture for ultra-low power MPSoCs., , and . Conf. Computing Frontiers, page 3:1-3:8. ACM, (2013)Configurable Low-Latency Interconnect for Multi-core Clusters., , , , and . VLSI-SoC (Selected Papers), volume 418 of IFIP Advances in Information and Communication Technology, page 107-124. Springer, (2012)Area and Power Modeling for Networks-on-Chip with Layout Awareness., , , , , , and . VLSI Design, (2007)A new physical routing approach for robust bundled signaling on NoC links., , and . ACM Great Lakes Symposium on VLSI, page 3-8. ACM, (2010)A low-overhead fault tolerance scheme for TSV-based 3D network on chip links., , , , and . ICCAD, page 598-602. IEEE Computer Society, (2008)Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing., , , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 102-111. Springer, (2011)3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory., , , , and . VLSI-SoC, page 30-35. IEEE, (2012)Synthesis of low-overhead configurable source routing tables for network interfaces., , and . DATE, page 262-267. IEEE, (2009)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster., , , and . DATE, page 1734-1739. IEEE, (2020)