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Disambiguation of "Lee, Dong Uk"

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Long-Term Chemical Aging of Hybrid Halide Perovskites

, , , , , , , , , and . Nano Letters, (July 2019)
DOI: 10.1021/acs.nanolett.9b02142

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Dong-Uk Kim

Uk Han Lee

Dong-Ki Lee

Dong Su Lee

Dong-Seup Lee

 

Other publications of authors with the same name

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV., , , , , , , , , and 7 other author(s). ISSCC, page 432-433. IEEE, (2014)Session 25 Overview: DRAM Memory Subcommittee., , and . ISSCC, page 342-343. IEEE, (2021)22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST., , , , , , , , , and 27 other author(s). ISSCC, page 334-336. IEEE, (2020)Long-Term Chemical Aging of Hybrid Halide Perovskites, , , , , , , , , and . Nano Letters, (July 2019)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)Design considerations of HBM stacked DRAM and the memory architecture extension., , , , , , and . CICC, page 1-8. IEEE, (2015)A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL., , , , , , , , , and 3 other author(s). ISSCC, page 547-556. IEEE, (2006)A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)