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A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer.

X. Liu, H. Krishnamurthy, R. Liu, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and V. De. ISSCC, page 478-480. IEEE, (2022)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Shetty

Vivek Bose

Other publications of authors with the same name

Reducing the data switching activity of serialized datastreams.M. Ghoneima, Y. Ismail, M. Khellah, and V. De. ISCAS, IEEE, (2006)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.M. Chang, J. Deguchi, V. De, M. Motomura, S. Shiratake, and M. Verhelst. ISSCC, page 506-508. IEEE, (2017)Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De. DAC, page 430-435. ACM Press, (1999)Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO.A. Singh, M. Kar, V. Chekuri, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay. IEEE J. Solid State Circuits, 55 (2): 478-493 (2020)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.R. Jain, B. Geuskens, S. Kim, M. Khellah, J. Kulkarni, J. Tschanz, and V. De. IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.R. Kumar, A. Varna, C. Tokunaga, S. Taneja, V. De, and S. Mathew. IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.G. Chen, M. Anders, H. Kaul, S. Satpathy, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy, V. De, and S. Borkar. IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors.C. Schaef, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De, N. Desai, H. Krishnamurthy, X. Liu, K. Ahmed, S. Kim and 3 other author(s). IEEE J. Solid State Circuits, 54 (12): 3316-3325 (2019)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De. IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.S. Vangal, S. Paul, S. Hsu, A. Agarwal, S. Kumar, R. Krishnamurthy, H. Krishnamurthy, J. Tschanz, V. De, and C. Kim. IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)

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