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Disambiguation of "Matsuzawa, Akira"

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A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC.

, , , and . IEEE J. Solid State Circuits, 51 (10): 2345-2356 (2016)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Hayashima

Akira Yasui

 

Other publications of authors with the same name

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator., , , , , and . IEEE J. Solid State Circuits, 45 (4): 697-706 (2010)A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration., , , , , and . IEEE J. Solid State Circuits, 49 (1): 50-60 (2014)A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC., , , and . IEEE J. Solid State Circuits, 51 (10): 2345-2356 (2016)A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio., , , , and . ASP-DAC, page 103-104. IEEE, (2008)A CMOS Smart Image Sensor LSI for Focal-Plane Compression., , , , , , , and . ASP-DAC, page 339-340. IEEE, (1998)Radio receiver front-end using time-based all-digital ADC (TAD)., , , , , , , , , and 3 other author(s). ICECS, page 471-473. IEEE, (2014)A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS., , and . ESSCIRC, page 151-154. IEEE, (2017)Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)Tunable CMOS Power Amplifiers for Reconfigurable Transceivers., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (11): 2394-2401 (2011)Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (8): 1518-1527 (2015)