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On a Class of Fault-Tolerant Multiprocessor Network Architectures.. ICDCS, page 302-311. IEEE Computer Society, (1982)High defect tolerant low cost memory chips., , and . SoCC, page 119-122. IEEE, (2007)Improved decoding algorithm for high reliable reed muller coding., and . SoCC, page 95-98. IEEE, (2007)ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management., and . JETC, 6 (2): 8:1-8:26 (2010)RTRAM: Reconfigurable and Testable Multi-Bit RAM Design., and . ITC, page 263-278. IEEE Computer Society, (1988)On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography., , , and . TQC, volume 5106 of Lecture Notes in Computer Science, page 96-104. Springer, (2008)Roll-Forward Checkpointing Schemes., , and . Hardware and Software Architectures for Fault Tolerance, volume 774 of Lecture Notes in Computer Science, page 95-116. Springer, (1993)Soft Error Mitigation in Switch Modules of SRAM-based FPGAs., , , and . ISCAS, page 141-144. IEEE, (2007)CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs., , , and . ISCAS, page 3675-3678. IEEE, (2007)Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off., and . IEEE Trans. Computers, 46 (3): 372-378 (1997)