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A memory allocation and assignment method using multiway partitioning., , и . SoCC, стр. 143-144. IEEE, (2004)SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces., и . CPA, том 68 из Concurrent Systems Engineering Series, стр. 287-302. IOS Press, (2011)High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog., и . CPA, том 63 из Concurrent Systems Engineering Series, стр. 275-288. IOS Press, (2005)Characterizing Sparse Connectivity Patterns in Neural Networks, , , и . (2017)cite arxiv:1711.02131Comment: Presented at the 2018 Information Theory and Applications Workshop, San Diego, California.Neural Network Training with Approximate Logarithmic Computations., , и . ICASSP, стр. 3122-3126. IEEE, (2020)Proteus: An ASIC Flow for GHz Asynchronous Designs., , и . IEEE Des. Test Comput., 28 (5): 36-51 (2011)Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning., , , и . ACML, том 129 из Proceedings of Machine Learning Research, стр. 273-288. PMLR, (2020)A polynomial time flow for implementing free-choice Petri-nets., , и . ICCD, стр. 227-234. IEEE Computer Society, (2012)High-performance asynchronous pipeline circuits., , и . ASYNC, стр. 17-28. IEEE Computer Society, (1996)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , и . ASYNC, стр. 124-131. IEEE Computer Society, (2015)